With feature size becoming smaller in circuit design, power leakage is becoming a more significant portion of the overall power consumed by a circuit, such as a sequential circuit. Power leakage in circuit design is an important issue, particularly because power leakage can account for a significant proportion of the total power for an IC.
For example, FIG. 1 illustrates a conventional device (e.g., inverter) 100 having an input a, an output nz, a voltage source, and ground. A capacitor 102 is charged by the supply current Vdd. Theoretically, once the capacitor 102 is charged, there will be no current flowing through the circuit and there will be no power leakage through the circuit. However, this may not be true in practice, since devices may leak. Even though a device is supposed to be turned off or inactive there can still be some current flowing/leakage through the device. Hence, there will be power leakage through the device.
This problem becomes more prevalent as technology shrinks and becomes faster. The smaller and faster the circuits are designed to operate, the greater the leakage. Thus, as the circuit density increases the leakage due to the increased devices also increases. It is desirable to reduce such leakage because it is occurring all the time irrespective of whether the device is performing an activity, or whether the central processing unit (CPU) of the device is on or off. As long as there is a power supply connected to the circuit, leakage can be occurring. Thus, leakage can account for a significant portion of the overall power consumed by an integrated circuit (IC) in an inactive state or with a significant number of inactive circuits.
This is not as much of a problem during activity, when the dynamic power is greater. However, if no activity is being performed, then the dynamic power is less (e.g., it may be zero). Thus, in an inactive state, the leakage current will dominate the total power of the IC. This is particularly problematic with battery powered devices in which the power supply is limited.
In low power circuit designs, it is desired to minimize the leakage current without sacrificing performance. For example, conventionally, a device can be added to the overall circuit to block the path from the voltage source to the circuit, or the path from the circuit to the ground, in order to limit or reduce the leakage through the circuit. In one conventional system, a global header or global footer is added in the power supply path from the voltage source to the circuit to limit the leakage. In other words, the power source is decoupled from the circuit to reduce leakage during inactivity of the circuits. A global header is a decoupling device that is coupled between Vdd and the circuit, while a footer is a decoupling device that is coupled between the circuit and Vss.
However, conventional global headers/footers have to be scaled to pass and control large currents and use additional control signals that are connected to numerous locations in the circuit design. Such design requirements result in increased costs, for example, in terms of area occupied by the circuit on the IC and increased routing complexity. Such conventional designs also may reduce the performance of the IC, for example, by reducing the speed of the circuit and reducing performance, as described in more detail below.
A high threshold voltage (high VT, or HVT) device is used in the conventional global headers and global footers to limit the leakage. Such high VT devices may not cut the leakage to zero. However, high VT devices can at least significantly reduce the leakage. This reduction in leakage is particularly the case in comparison to low threshold voltage (low VT, or LVT) circuits which may be used in the operational circuits supplied by the header or footer. Conventionally, either a global header or a global footer is used, since a combination of global headers and global footers is redundant and provides no substantial benefit. Also, the additional headers/footers can further increase the area and cost of the circuit.
Additionally, conventional systems that use a global header or footer can be undesirable because the global header/footer acts like a resistance in series. Accordingly, each time the conventional circuit draws a current, the current passes through the header/footer, which is equivalent to being a resistor in series, thereby reducing efficiency and performance of the circuit. Thus, instead of having Vdd/Vss directly supplied to the circuit, the header circuit is turned on and charged, which can result in an increase in the overall power consumption during operation, as the global header/footer is scaled to supply large currents drawn by many circuit elements coupled to the global header/footer.
Additionally, a conventional system that uses a global header or footer may have substantial voltage/current spikes resulting from turning on the large global header/footer needed for the circuits to be coupled/decoupled to the power supply. Thus, some conventional systems use different ways to turn on the global header/footer to avoid spiking. For example, some conventional systems turn on the header/footer using an intermediary device to ramp up the voltage to avoid spikes and noise spikes at Vdd and VVdd. This can take a few cycles depending on the circuit configuration and further increases the overall system complexity. This conventional method is also undesirable because there is a wake-up time associated with this method.
For at least the foregoing reasons, the conventional global headers or footers can be expensive to implement, and can degrade performance significantly. Other conventional systems which use two power sources (i.e., one power source for high VT devices and another power source for low VT devices) are not practical or desirable because such configurations dramatically increase the cost of the circuit design, for example, in terms of area, complexity, having multiple power grids, etc.
Other conventional systems use high VT devices to try to limit or reduce leakage, since such devices require substantially greater voltage to turn on, and thus, may leak less than low VT or regular threshold voltage devices. However, the performance of high VT devices can be substantially lower than low VT or regular VT devices. Although, if performance is not an issue for a particular application, a high VT device may be suitable. Further, high VT devices do not work very well (i.e., satisfactorily) at low voltage because of the higher threshold voltage. Once the voltage is lowered, the devices do not work very well, if at all. Thus, high VT devices may not be a practical alternative for reducing or limiting leakage, in many (if not, most) applications.
For at least the reasons set forth above, conventional global headers and footers can be very expensive and require an additional (or dedicated) control signal to be connected to numerous locations in the circuit design, which increases the cost, for example, in terms of area occupied by the circuit on the IC. Such conventional designs also can increase the cost with respect to the performance of the IC, for example, by reducing the speed of the circuit and reducing performance.
Accordingly, there is a need for a method and system for reducing leakage while maintaining performance of a circuit.